John Palmour, CTO at Cree, sat down with Semiconductor Engineering to talk about silicon carbide, how it compares to silicon, what’s different from a design and packaging standpoint, and where it’s being used. What follows are excerpts of that conversation.
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SE: SiC is well-understood in power electronics and RF, but is the main advantage the ability to run devices hotter than silicon, or is it to save energy?
Palmour: The goal is to save energy and reduce system costs. Silicon carbide saves the OEM money.
SE: Right up front?
Palmour: Yes. For instance, if you say, ‘Okay, I can put in silicon carbide, which is more expensive than an IGBT but I can save three times that on battery cost, that’s what they do.’ More often than not being used for upfront cost.
SE: But that’s not necessarily a one-to-one saving on material. It’s more about the system cost, right?
Palmour: Yes, absolutely. Silicon carbide is more expensive than silicon IGBTs, and the places we get our wins is where they realize the savings at the system level. It’s almost always a system sell.
SE: Has that slowed the adoption of SiC?
Palmour: You have to find the applications where you save money at the system level. But as you do that and start shipping volume, the price comes down and you start opening up other applications. In the past, the limiting factor was the up-front cost, but people are starting to look a lot more at system costs and they realize the up-front cost from that perspective is better with silicon carbide.
SE: How about availability of SiC versus silicon?
Palmour: If you’re an automotive OEM, you do worry about capacity because the impact of these automotive designs will be to drive the market to become a lot larger than it is today. Assurance of supply is a concern. That’s why Cree announced numerous wafer supply agreements with other companies that make silicon carbide devices. We did an announcement with Delphi, where we sell chips to Delphi and they sell an inverter to a European OEM. Those things are getting looked at, and you have to lock in supply. On these long-term purchase agreements, we have to know that demand will be there before we invest a lot of capital for capacity. We announced last year we’re adding $1 billion of CapEx to greatly increase our capacity to meet this need. It’s required, and it’s just a start. If you run the numbers on the penetration of battery electric vehicles to the overall vehicle market, this is just beginning.
SE: Is this all 200mm, or is it older technology?
Palmour: The bulk of all production today is on 150mm 6-inch wafers. There is still some on 4-inch. We’re building a new fab in New York that will be 200mm-capable, but we’re not doing any 200mm today and aren’t expecting to be ready for that for several years. When 8-inch is ready, we can turn it on. The equipment is all going to be 200mm so that we can rapidly move it over to 8-inch when the time is right. There is no 8-inch in production today.
SE: Is the process radically different from silicon chip manufacturing? Does it utilize the same tools you would normally use?
Palmour: If you’re talking materials growth, it’s different. Crystal growth is radically different. Wafering, polishing, epitaxy are all quite different. But once you get into the fab, it’s fairly standard equipment with the exception of two or three processes, which are heavily tailored to silicon carbide. The fundamental fab processes are very silicon-like, and the bulk of the clean-room equipment is typical silicon equipment.
SE: How about on the test and inspection side?
Palmour: Those are quite similar to silicon.
SE: Because SiC is run at higher temperatures, is defectivity more of a problem?
Palmour: The reason silicon can’t go to very high temperatures is because intrinsically it starts to conduct. It really stops being a semiconductor around 175°C, and by 200°C it becomes a conductor. For silicon carbide that temperature is much higher — about 1,000°C — so it can operate at much higher temperatures. But we’re not targeting much higher temperatures than silicon because of the packaging. The higher the temperature at which you rate your package, the larger the delta T between low temp and high temp and the faster your package can degrade. We’re not going for radically higher temperature. And in fact, because we’re efficient, we actually don’t get that hot on a per-square-centimeter basis. Our chips are typically going for about 175°C, which is not all that much higher than silicon.
SE: That puts SiC into the ASIL D category for automotive or industrial applications, right?
Palmour: Yes, absolutely.
SE: What’s different on a physics level?
Palmour: Silicon has a bandgap of 1.1 electronvolts, and that is basically the definition of how much energy it takes to rip an electron out of the bond between two silicon atoms. So it takes 1.1 electronvolts to yank an electron out of that bond. Silicon carbide as a band gap of 3.2 electronvolts, and so it takes 3 times more energy. But it’s actually an exponential function. A lot of the characteristics of semiconductors bandgap are actually up in the exponent. We’ve got three times wider bandgap, but when it comes to electric breakdown we actually have 10 times higher electric breakdown field.
SE: What does that mean in terms of real-world applications?
Palmour: It means that if you make the exact same structure in silicon and silicon carbide — the same epi thickness, the same doping level — the silicon carbide version will block 10 times more voltage than the silicon version. You can make a MOSFET in silicon and you can make a MOSFET in silicon carbide. MOSFETs in silicon are very common in the low-voltage region, from 10 volts up to about 300 volts. Above 300 volts, the resistance of a silicon MOSFET gets very very high and it makes the MOSFET unattractive. It’s too expensive. So what they do is they switch over to a bipolar device. A MOSFET is a unipolar device, meaning there’s no minority carriers. There are only electrons flowing in the device. And when it’s a unipolar device, it can switch very, very fast. If you look at a 60-volt MOSFET, it switches very fast, and that’s, that’s why you can make gigahertz processors in silicon. They’re very low voltage MOSFETs — maybe 5 volts. But when you get up higher in voltage you have to go to a bipolar device, meaning that both electrons and electron holes are flowing in the device at the same time. And every time you switch, you have to dissipate all those electrons and holes recombining and generating energy. The bipolar device gives you much lower resistance and a much smaller, more affordable chip, but you’ve got to dissipate that excess heat every time you switch. That’s the tradeoff you’re making. You can make an affordable power switch, but it’s not very efficient.
Fig. 1: SiC MOSFET. Source: Cree
SE: How about with SiC?
Palmour: Silicon carbide has a 10 times higher breakdown field. Our 600-volt MOSFET is going to be as fast as a 60-volt silicon MOSFET. The other way to look at it is if you say 600 volts is the voltage at which you switch from MOSFETs and silicon over to IGBTs, we would be at 10 times higher voltage. So you would use a MOSFET in silicon carbide up to 6,000 volts before you had to switch to an IGBT. The high electric breakdown field that we get from this wide bandgap allows us to use the device type that you would want to use in silicon, but you can’t because it’s too resistive to make it practical. So you can make the device in silicon carbide that you really wanted in silicon, but due to the physics of silicon it isn’t practical in that voltage range.
SE: Does the silicon carbide age the same as silicon due to the higher voltage?
Palmour: It’s the same. Voltage doesn’t matter. It’s the electric field, which is the same regardless of the voltage. Silicon carbide is very rugged, and it doesn’t age any differently than any other semiconductor.
SE: Will there be economies of scale as SiC gets used in more places?
Palmour: Yes. It will be a little more asymptotic than Moore’s Law because of the thermal considerations, but we are definitely early in the cost-down curve. From to , we expect volume to increase by 30X. That will have an impact.
SE: Any constraints that could disrupt that increase in volume?
Palmour: Silicon carbide is sand and coal. Silicon and carbon are two of the most abundant elements on earth. It’s not like indium phosphide or hafnium. I worry more about whether battery electric vehicles can get enough lithium, and whether there are enough rare earths to do the permanent magnet motors. We can make the semiconductors.
SE: We’re now seeing much more attention focused on multiple chips in a package. How does SiC behave in those types of packages? Would it necessarily even be in the same package?
Palmour: In terms of silicon carbide power devices, we have three product lines. One is discrete power devices. So it’s a single MOSFET in a TO-247, or a diode in a TO-220 package — just a typical standard discrete package. And then we sell chips to other companies that are going to do their own package, but by and large those are module manufacturers. And then we have our own modules. A module includes multiple silicon carbide MOSFET chips in parallel, to get more power, in a very simple circuit. In the most common cases, it’s other identical silicon carbide chips in that power module. Let’s say you have a 100-amp chip, but you need a power module and an H-bridge configuration that gives you 600 amps. So you’d put six 100-amp devices on one side, six 100-amp devices on the other to give you that H-bridge, and then maybe some capacitors or some resistors. That is in the market today. The big issue — and what we do a lot of work on and what a lot of the guys working on automotive are working on — is if you were to drop our chips into a standard silicon power module package, you’d only be getting about half of the performance that the chips could give you because of the built-in inductances. I would equate it to dropping a Ferrari engine into a VW bug chassis.
SE: That sounds like a mismatch.
Palmour: What we and others are working on is how to optimize that module to take full advantage of silicon carbide. We have to build a Ferrari chassis for that engine, and that’s what’s being worked on in power modules. As for whether it would work with other chips in a package, the answer is yes. Typically today, the drivers and other chips that make up this power module are on a board. Usually it’s on a separate board placed right beside that module, but it could be in the same module. It’s called an intelligent power module. But you definitely can do the same in silicon carbide.
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SE: How about things like noise and drift, which are growing problems in many designs? Is it any different with SiC?
Palmour: There are two parts to that question. In terms of stability of the oxides, there is some drift in silicon carbide. We spend a lot of time working on that minimizing it. It’s not a problem once you get it right. It’s really mostly time of operation. It will basically shift in the first 10 or 20 hours, and then it will stabilize. And if you turned everything off it would happen again, so the solution is to make that as minimal as possible. In terms of noise, we’re not so susceptible to noise like other chips. But because silicon carbide can be operated at such high frequencies, and can switch at really high dv/dt and di/dt, we actually create noise. You have to do your circuit design very carefully to minimize how much noise you generate.
SE: Does shielding help?
Palmour: It’s really not shielding as much as it is getting your design right. In silicon, you could put the driver a foot away and pipe a cable and it’s no big deal. In silicon carbide you’d have so much inductance it would ring like a like a banshee. You have to put the driver up very close to the module to minimize that inductive ringing and reduce noise. You need to keep those inductances minimal.
SE: So this heads into the big problem RF designers are dealing with today, right?
Palmour: Right, and we do both RF and power. When you use silicon carbide, it’s pushing you more towards the RF realm than a lot of people in power are used to thinking. RF is a different world. Capacitors become resistors, resistors become capacitors, and everything turns upside down.
SE: But SiC has been used extensively in the RF world, right?
Palmour: Yes, and RF is the other part of our business. There we use SiC as a substrate. We used to sell SiC MESFETs (metal-semiconductor FETs) for RF devices. For Gan RF, 99% of the Gan RF devices out there are done on a silicon carbide substrate.
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Over the past decade, the incorporation of Silicon Carbide (SiC) in power, LED, and RF devices has steadily increased, allowing for this technology to progressively mature in all aspects. This is due to the many desirable qualities this wide-bandgap substrate has relative to its silicon (Si)-based counterparts — the ability to achieve much higher power per given die size, at much faster switching speeds, and with excellent thermal performance.
Contrary to popular opinion, all of these characteristics actually lead to the employment of fewer power devices, magnetics, and respective gate drivers, actually yielding a lower system cost when compared with Si-based high-power designs (e.g., OBCs, string inverters). From growing the boules to the fabrication and device packaging, the stringent qualification process for SiC devices has been thoroughly developed. Moreover, with over 30 years of legacy in SiC, Wolfspeed power devices have experienced over 6 trillion field hours — reaching a point at which data on long-term reliability can be adequately ascertained.
This article dives into the qualification process of SiC components and how this yields high extrinsic device reliability while looking into the accumulated data on long-term wear-out for SiC. There is an additional discussion regarding industry capacity and continuity of supply to support the ever-growing demand for SiC-based devices.
The SiC power device has steadily infiltrated a number of industry verticals for power devices from solar power conversion, power grid systems, industrial motor conversion, and on-board charging for EVs. The proliferation of SiC-based MOSFETs and diodes are for a good reason — when compared with standard Si-based power devices (e.g., IGBTs, SJ MOSFETs), SiC devices offer half the losses, at a third of the size, and with 20% lower system costs. The higher power conversion per die size is due to the fact that SiC has nearly 3× the bandgap, 10× the breakdown electric field, over 2× the thermal conductivity, and 5× the power density when compared with Si.
As more and more designers are currently, or have in the past, designed with SiC, several fundamental long-term effectiveness questions based on SiC quality, reliability, and supply crop up. Some frequently asked questions include:
These are critical questions for vendors to ask in order to position themselves strongly within the power device market long term. The Si substrate has a familiarity within the industry from its fabrication to packaging and device-level completion — the technology has been able to mature over 60 years in the fab and the field. However, this does not outweigh SiC in the power device market. Wolfspeed has over 30 years of legacy with SiC, from delivering the world’s first SiC MOSFET in to being the only vertically integrated SiC manufacturer from growing the SiC boules to packaging die — all while steadily driving up voltage and current ratings, increasing wafer diameters to bring down cost per unit, and meeting stringent industry and automotive qualifications. The massive benefit of this focused effort over three decades? The collection of relevant data to perform in-depth reliability analysis comparable with that of Si.
Reliability engineers are familiar with the basic bathtub curve to understand the varying regions of device failures (Figure 1). The first region (Region I) of the bathtub curve includes wear-in failures, or “infant mortality,” and is often dependent on rigorous device qualification. Region II of the bathtub curve relates to the steady state, or field failure rate with constant (random) failures such as external stressors that lead to failures. Finally, Region III of the curve relates to long-term wear-out of the device with accumulation of damage over time. Each of these regions of the bathtub curve correlate to different types of deterioration modeling. In other words, the three areas that the market cares about involve the following:
For the power device, the first region relies on qualification testing. The second region relies on device hours (e.g., 1,000 hours, 10,000 hours, 1 million hours) in the field to accumulate sufficient data to acquire a failure in time (FIT) rate. The third region relies on lifetime prediction models and mean time to failure (MTTF) calculations.
SiC MOSFETs involve several salient features that, when optimized, offer high quality and more reliability. These include:
The two potential failure modes of a SiC device are related to blocking voltage and gate voltage. Figure 2 shows the common failure mechanisms in SiC devices as well as some industry reliability tests to ensure proper operation of the MOSFET.
Gate oxide breakdown can occur in SiC MOSFETs due to the smaller thickness of the gate oxide layer combined with the application of a higher electric field relative to Si-based devices. This can cause the threshold voltage to increase over long periods of time. However, this problem is sidestepped when MOSFET gate voltage is regularly switched between on and off states as the threshold voltage reverses during the switch.
In planar structures, breakdown voltages at planar junctions can limit the potential reverse-bias blocking capability of SiC MOSFETs due to an electric field crowding effect. With this effect, the electric field becomes spatially non-uniform and causes crowding at the device periphery. Effective edge termination structures can mitigate this effect and increase device reliability. In most devices, the blocking voltage does not reach the ideal breakdown value for one of two reasons: defects in the active area or the electric field crowding effect. There is, however, a balancing act between edge termination length (termination area) and material cost. It is therefore optimal to strike a balance between the two.
The electrical and thermal performance of the interconnect in power devices become more challenging as device dimensions become smaller. The intermetal dielectric (IMD) breakdown relates to the IMD leakage current that occurs in the event of dielectric breakdown due to a high voltage pulse or continuous power. This is typically tested with the time-dependent dielectric breakdown (TDDB) test in order to screen out defect-related breakdowns that can lead to infant mortality.
More often than not, the random failure mechanism for an already-qualified SiC device would be due to cosmic radiation. Terrestrial neutron irradiation occurs when neutrons collide with lattice atoms in the power device; this causes atoms to recoil and protons and/or neutrons to be emitted. Charges spike along these trajectories, leaving ionization trails that are not negligible — on the order of micrometers, which is comparable with epilayer thickness. The current transients that are induced by the neutron collision can cause failures in both bipolar and MOSFET-type SiC devices. In the bipolar NPN, bipolar turn-on can occur, causing burnout. In the MOSFET, charge accumulation can occur, causing a gate oxide failure.
The SiC device has an intrinsically higher reliability when compared with Si counterparts (e.g., IGBTs) due to the relatively smaller die size — there is far less physical area to get hit with a neutron bomb. As demonstrated by the graph in Figure 3, the failure rates increase proportionally with device area while the failure rates also decrease as voltage rating increases. This is the main failure mechanism at steady-state, particularly for high-altitude applications such as aerospace, high-altitude power installations, or even an EV driving around a mountain.
With these common failure mechanisms in mind, Wolfspeed utilizes proven industry-standard testing to ensure the SiC devices are of the utmost quality prior to releasing them (Figure 2). This includes the qualification testing across large samples sizes in different lots to ensure a 90% confidence, or <1% failure rate. The product qualification that the SiC devices undergo ensures a high extrinsic reliability.
Wolfspeed leverages industrial (JEDEC) and automotive standards (AEC-Q101) that were constructed around silicon. The AEC-Q101 standard is generally more stringent than the JEDEC: The automotive standard requires 77 samples to be tested across three separate lots, while the JEDEC industrial standards require 25 samples across three lots. The AEC standards require the high levels of electrical and optical screening available and also monitor drift and shift within the lots under test. The major industry consortia including JEDEC, IEC, AEC, and JEITA are all actively developing SiC-specific standards to meet the needs for SiC technology and customer base. Wolfspeed is integrally involved in this process, working with subcommittees and task groups on SiC reliability and qualification testing.
Typically, a higher failure rate is seen at the extrinsic part of the bathtub curve, as this is the stage where faulty components are screened out. Table 1 lists the typical product qualification that a SiC device undergoes at Wolfspeed. Table 2 lists how these stress tests relate to performance for devices that require a high drain bias, high altitude, high humidity, high gate bias, or third-quadrant operation — each of these requirements relate to specific potential failure mechanisms. A high blocking voltage requires a high electrical field reliability, while a high gate oxide voltage needs a high gate oxide reliability. A high switching speed necessitates a high threshold voltage (VGS(th)) stability, high body diode is requisite for third-quadrant operation, and finally, there is a need for high terrestrial neutron reliability for high-altitude applications.
As stated earlier, Wolfspeed’s legacy in SiC has allowed the compilation of massive amounts of data — over 6 trillion field hours. From this data, FIT rate analysis has been performed on various Wolfspeed SiC devices, as shown in Table 3. While qualification is paramount to ensure basic field reliability, the failures that occur post-qualification truly dictate the viability of the supplier and the quality of the technology. The FIT rates are calculated according to industry standards, wherein the first three months of sale are discounted, the actual field hours are ascertained by factoring in when the device is not being used, and the failures due to cosmetic reasons (e.g., part returns) are discounted from the calculation for accuracy.
As seen in the table, the Wolfspeed FIT rates are typically below 5% ppb and decrease with an increase in field device hours. For this reason, the C6D diode appears to have the highest FIT rate, as it is at the tail end of the extrinsic part of the bathtub curve as a relatively new product.
The reliability testing of SiC devices and the various lifetime prediction models reveal the typical failure mechanism as the device ages. Wolfspeed employs common testing techniques for intrinsic wear-out by pushing the device to way over the maximum voltage rating or current rating for as long as possible and under the worst conditions possible. In Figure 4, a 1,200-V–rated Wolfspeed MOSFET is pushed up to 1,700 V and predicted hours of operation are obtained based upon this stress.
It should be noted that a 1,200-V–rated Si device generally rolls out at about 1,250 V; therefore, SiC devices generally have much more margin on their voltage ratings. Typically, a 1,200-V–rated SiC MOSFET is working on a 700- to 800-V bus — in this case, there are over 300 million hours of theoretical safe operation before the device fails from a failure mechanism due to blocking voltage. The very same process is applied to gate voltage with the TDDB method.
The TDDB method is another method of understanding the MTTF of power devices. This method subjects a population of MOSFETs to a constant bias at accelerated bias conditions as well as elevated temperatures. The failure time statistics are calculated and Weibull distributions are fit to the failure statistics to estimate lifetime. In Figure 4, a device with a gate voltage rating of 15 V is pushed to beyond 35 V and the probability of failure at the rated gate voltage becomes 50 million device hours. For the Gen3 650-V Wolfspeed MOSFETs, the MTTF stands at 70 million hours at 15-V continuous gate bias, showing a nearly identical gate reliability to the 1,200-V and 1,700-V MOSFETs.
In order to accurately assess all regions of the bathtub curve for their SiC devices, Wolfspeed developed a bathtub curve calculator that uses a mission profile as input. As shown in Figure 5, this profile is based upon field, qualification, and testing parameters such as VG, VD, TJ, altitude, and an hours histogram.
While much work is done to ensure the successful operation of a bare die SiC, the power and packaging is an unavoidable reliability issue for both Si and SiC alike. Typically, power packaging is the weakest link, especially at higher temperatures where the failures tend to be more intrinsic in nature (e.g., wire bonds and die attach rip off) The industrial power cycling test is the standard way to characterize the wire bond thermomechanical fatigue wear-out mechanism. It has been shown that the reliability performance is comparable between SiC and Si devices and that failures occur due to thermomechanical fatigue for both types of devices regardless of substrate material.
Now that it is well established that SiC is both high-quality and high-reliability, with sufficient data to prove so, the question then pivots to the ability to supply these devices. Wolfspeed is fully invested in meeting present and future demand with a billion-dollar investment in the largest state-of-the-art dedicated SiC fabrication facility. This allows for 30× the original capacity of Wolfspeed, meeting the predicted world market growth of a tenfold increase in SiC semiconductors from to . This is a considerable growth in capacity when compared with other market suppliers of this semiconductor, wherein the closest supplier comes in to serve approximately $720 million of the $2.4 billion market estimate — meeting only a fraction of the capacity capability that Wolfspeed has (Figure 6).
SiC semiconductor applications are expanding greatly due to their excellent performance, power capacity, efficiency, die size, and relative cost-effectiveness. With over 30 years to compile past and present data, there is a large swath of information that allows for FIT rate analysis and extrinsic characterization, ensuring that SiC products are of high quality. This momentum is pushing standards committees to develop and evolve SiC-specific industrial standards, allowing for the continued maturity and utilization of SiC technology. Long-term wear-out and reliability analysis is continually being performed to better assess the failure mechanisms of these devices due to aging, and while it is not as established as Si devices that have had over 60 years of legacy, this data is maturing for more accuracy and dependability.
Wolfspeed is a leading vendor in SiC technology as the only vertically integrated SiC manufacturer with a significant investment in ensuring any and all SiC devices are robust prior to launch. This has also allowed for the continual progression of a strong support ecosystem with design software and tools to implement SiC.
With 6 trillion field hours of data to build upon, extended wear-out studies, and FIT rates in the single digits, Wolfspeed is leading the way on quality, long-term reliability, and safe use of SiC devices.
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